Mems inertial power generators for biomedical applications

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Improving the power-delay performance in subthreshold source-coupled logic circuits

Subthreshold source-coupled logic (STSCL) circuits can be used in design of low-voltage and ultra-low power digital systems. This article introduces and analyzes new techniques for implementing complex digital systems using STSCL gates with an improved power-delay product (PDP) based on source-follower output stages. A test chip has been manufactured in a conventional digital 0.18$\mu$m CMOS technology to evaluate the performance of the proposed STSCL circuit, and speed and PDP improvements by a factor of up to 2.4 were demonstrated

Digital Signal Processing Research Program

Contains table of contents for Section 2, an introduction, reports on twenty-two research projects and a list of publications.Sanders, a Lockheed-Martin Corporation Contract BZ4962U.S. Army Research Laboratory Contract DAAL01-96-2-0001U.S. Navy - Office of Naval Research Grant N00014-93-1-0686National Science Foundation Grant MIP 95-02885U.S. Navy - Office of Naval Research Grant N00014-96-1-0930National Defense Science and Engineering FellowshipU.S. Air Force - Office of Scientific Research Grant F49620-96-1-0072U.S. Navy - Office of Naval Research Grant N00014-95-1-0362National Science Foundation Graduate Research FellowshipAT&T Bell Laboratories Graduate Research FellowshipU.S. Army Research Laboratory Contract DAAL01-96-2-0002National Science Foundation Graduate FellowshipU.S. Army Research Laboratory/Advanced Sensors Federated Lab Program Contract DAAL01-96-2-000

Subthreshold FIR Filter Architecture for Ultra Low Power Applications

Subthreshold design has been proposed as an effective technique for designing signal processing circuits needed in wireless sensor nodes powered by sources with limited energy. In this paper we propose a subthreshold FIR architecture which brings the benefits of reducedleakage energy, reduced minimum energy point, reduced operating voltage and increased operating frequency when compared with recently reported subthreshold designs. We shall demonstrate this through the design of a 9-tap FIR filter operating at 220mV with operational frequency of 126kHz/sample consuming 168.3nW or 1.33pJoules/sample. Furthermore, the area overhead of the proposed method is less than that of the transverse structure often employed in subthreshold filter designs. For example, a 9-tap filter based on transverse structure has 5X higher area than the filter designed using our proposed method

A Resonant 1:5 Cockcroft-Walton Converter Utilizing GaN FET Switches with N-Phase and Split-Phase Clocking

Recent demonstrations of merged inductor-capacitor (LC) switching converters have resulted in record power densities being achieved at high voltage conversion ratios. To do so, sophisticated switch control schemes may be required. This work demonstrates N-phase and Split-phase switching techniques applied to a resonant Cockcroft-Walton converter. For the same hardware, the lower resonant switching frequency of the N-phase scheme significantly improves light-load efficiency relative to the Split-phase scheme. However, the N-phase approach suffers reverse body diode turn-on at large voltage ripple contributing to the Split-phase scheme obtaining the highest power density. Converter performance combining both switching techniques is analyzed using a discrete 1:5 Cockcroft-Walton converter implemented using gallium nitride FETs, multi-layer ceramic chip (MLCC) capacitors, and a 68 nH inductor. The resulting converter achieves a peak efficiency of 94.9% and 94% for the N-phase and Split-phase schemes respectively with the N-phase scheme seeing a 30% reduction in losses at light-load. The converter achieves a maximum output power of 190W, resulting in a record power density of 483.3 kW/liter (7,920 W/inch3) and specific power of 243 kW/kg

Reducing COSSSwitching Loss in a GaN-based Resonant Cockcroft-Walton Converter Using Resonant Charge Redistribution

By applying resonant charge redistribution (RCR) to the parasitic capacitances of a switched-capacitor converter, COSS-related dynamic switching losses can be significantly reduced. The proposed technique demonstrates adiabatic mitigation of all primary loss mechanisms in a transformer-less resonant Cockcroft-Walton (CW) converter's forward power path, with only the gate drivers exhibiting conventional hard-charged CV2f losses. Two inductors are used: a large primary inductance directly in the forward power path to mitigate transient inrush currents, and a second small inductance to perform Coss charge redistribution prior to initialization of subsequent phases. The second inductor can be small while still exhibiting high Q-factor as it only interacts with switch parasitics. A discrete 1:5 prototype using GaN-FETs and diodes achieves a power density of 181.8 kW/liter (2.98 kW/inch3) and a peak efficiency of 96.2% with RCR contributing a measured 61% reduction in total losses at light load for a 0.74% increase in solution volume